One aspect of designing an integrated circuit (IC) is that of routing signal buses from one part of the IC to another part of the IC to electrically connect circuit elements. The routing of a signal bus (i.e., a bus) may involve traversing many layers of the IC. Furthermore, in a congested IC design, there are many elements that can serve as obstacles to routing a bus. Such obstacles have to be avoided when routing the bus from a source location to a destination location of the IC design. As a result, the task of routing a bus for an IC design can be very complex, especially when a bus has dozens or hundreds of bits (i.e., when the bus is a wide bus).
Routing of buses (especially wide buses) is accomplished largely through manual manipulation of the circuit design by a human designer. The human designer may have to go through many iterations of routing a bus, in a trial-and-error manner, before arriving at an acceptable solution that takes into account various bus-routing constraints such as signal timing and delay. This can be very time-consuming. Even when the human designer arrives at an acceptable solution for routing a bus from an operational perspective, the solution may still be sub-optimal from an IC real-estate utilization perspective. That is, the human designer may have wasted valuable space on the IC that could have been used for the subsequent routing of other buses that are to be routed on the IC. However, the human designer may not realize that there is a more optimal solution.